Registers
329
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.2.4
CIG_reg3 Register (offset = Ch) [reset = 0h]
CIG_reg3 is shown in
and described in
.
CIG HDMI Transparent Color
Figure 1-222. CIG_reg3 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
TR_COLOR
R/W-0h
15
14
13
12
11
10
9
8
TR_COLOR
R/W-0h
7
6
5
4
3
2
1
0
TR_COLOR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-129. CIG_reg3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
Reserved
R
0h
Reserved
23-0
TR_COLOR
R/W
0h
Transparency Color 23:16 R 15:8 G 7:0 B (If the video pixel matches
this color while transparency is enabled, the alpha value is forced to
0.)
