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Registers
855
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.37 SD_VENC_cvrclp Register (offset = FCh) [reset = 180007FFh]
SD_VENC_cvrclp is shown in
and described in
CVBS V Clip
Figure 1-532. SD_VENC_cvrclp Register
31
30
29
28
27
26
25
24
Reserved
CVLCLP
R-0h
R/W-1800h
23
22
21
20
19
18
17
16
CVLCLP
R/W-1800h
15
14
13
12
11
10
9
8
Reserved
CVUCLP
R-0h
R/W-7FFh
7
6
5
4
3
2
1
0
CVUCLP
R/W-7FFh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-448. SD_VENC_cvrclp Register Field Descriptions
Bit
Field
Type
Reset
Description
31-29
Reserved
R
0h
28-16
CVLCLP
R/W
1800h
CVBS V Lower Limit. s12.0
15-13
Reserved
R
0h
12-0
CVUCLP
R/W
7FFh
CVBS V Vpper Limit. s12.0