Texas Instruments DM38x DaVinci, User Manual

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Registers
397 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
Table 1-182. intc_intr1_ena_set0 Register Field Descriptions (continued)
Bit Field Type Reset Description
16 VPDMA_INT1_DESCRIP
TOR_ENA_SET R/W 0h
VPDMA INT0 Descriptor Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
15 VPDMA_INT1_LIST7_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List7 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
14 VPDMA_INT1_LIST7_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List7 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
13 VPDMA_INT1_LIST6_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List6 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
12 VPDMA_INT1_LIST6_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List6 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
11 VPDMA_INT1_LIST5_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List5 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
10 VPDMA_INT1_LIST5_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List5 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
9 VPDMA_INT1_LIST4_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List4 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
8 VPDMA_INT1_LIST4_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List4 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
7 VPDMA_INT1_LIST3_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List3 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
6 VPDMA_INT1_LIST3_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List3 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
5 VPDMA_INT1_LIST2_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List2 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
4 VPDMA_INT1_LIST2_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List2 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
3 VPDMA_INT1_LIST1_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List1 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
2 VPDMA_INT1_LIST1_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List1 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect
1 VPDMA_INT1_LIST0_NO
TIFY_ENA_SET R/W 0h
VPDMA INT0 List0 Notify Enable/Set Read indicates interrupt enable
0 = disabled 1 = enabled Writing 1 will set interrupt enabled Writing 0
has no effect
0 VPDMA_INT1_LIST0_CO
MPLETE_ENA_SET R/W 0h
VPDMA INT0 List0 Complete Enable/Set Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will set interrupt enabled
Writing 0 has no effect