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Registers
759
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.5
HD_VENC_D_cfg4 Register (offset = 10h) [reset = 0h]
HD_VENC_D_cfg4 is shown in
and described in
Color Space Converter Coefficient Register
Figure 1-441. HD_VENC_D_cfg4 Register
31
30
29
28
27
26
25
24
Reserved
B2
R-0h
R/W-0h
23
22
21
20
19
18
17
16
B2
R/W-0h
15
14
13
12
11
10
9
8
Reserved
A2
R-0h
R/W-0h
7
6
5
4
3
2
1
0
A2
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-354. HD_VENC_D_cfg4 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-29
Reserved
R
0h
Reserved
28-16
B2
R/W
0h
Coefficients of color space converter. This coefficient is a real
number in the range of -4 to +4 represent in Q3.10 format. The MSB
is sign bit. (Same format conversion as A0 in HD_VENC_D_cfg1)
15-13
Reserved
R
0h
Reserved
12-0
A2
R/W
0h
Coefficients of color space converter. This coefficient is a real
number in the range of -4 to +4 represent in Q3.10 format. The MSB
is sign bit. (Same format conversion as A0 in HD_VENC_D_cfg1)