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Registers
890
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.14.2 VIP_PARSER_port_a Register (offset = 4h) [reset = 0h]
VIP_PARSER_port_a is shown in
and described in
.
Configuration for Input Port A
Figure 1-564. VIP_PARSER_port_a Register
31
30
29
28
27
26
25
24
analyzer_fvh_err_corr
ection_enable
ANALYZER_2X4X_S
RCNUM_POS
FID_SKEW_POSTCOUNT
R-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
SW_RESET
DISCRETE_BASIC_M
ODE
FID_SKEW_PRECOUNT
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
USE_ACTVID_HSYN
C_N
FID_DETECT_MODE
ACTVID_POLARITY
VSYNC_POLARITY
HSYNC_POLARITY
PIXCLK_EDGE_POL
ARITY
FID_POLARITY
ENABLE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
CLR_ASYNC_FIFO_
RD
CLR_ASYNC_FIFO_
WR
CTRL_CHAN_SEL
SYNC_TYPE
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-482. VIP_PARSER_port_a Register Field Descriptions
Bit
Field
Type
Reset
Description
31
analyzer_fvh_err_correctio
n_enable
R/W
0h
Embedded Sync Only
0 = Ignore the protection bits in the XV (fvh) codeword header. This
setting is typically desired.
1 = Use the protection bits in an attempt to do error correction for the
fvh control bits.
30
ANALYZER_2X4X_SRCN
UM_POS
R/W
0h
Embedded Sync Only
0 = For 2x/4x mux mode.. srcnum is in the least significant nibble of
the XV/fvh codeword (srcnum replaces the protection bits)
1 = For 2x/4x mux mode.. srcnum is in the least significant nibble of
a horizontal blanking pixel value
29-24
FID_SKEW_POSTCOUN
T
R/W
0h
Discrete Sync Only post count value when using vsync skew in FID
determination
23
SW_RESET
R/W
0h
0 = Normal
1 = Reset Port A logic. Must be set to '0' again by the software for
the module to function.