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Registers
434
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.34 intc_intr3_ena_clr1 Register (offset = 9Ch) [reset = 0h]
intc_intr3_ena_clr1 is shown in
and described in
Interrupt3 Enable/Clear Register 1
Figure 1-290. intc_intr3_ena_clr1 Register
31
30
29
28
27
26
25
24
Reserved
VIP2_CHR_DS_2_UV
_ERR_INT_ENA_CLR
VIP2_CHR_DS_1_UV
_ERR_INT_ENA_CLR
R-0h
R/W-0h
R/W-0h
23
22
21
20
19
18
17
16
VIP1_CHR_DS_2_UV
_ERR_INT_ENA_CLR
VIP1_CHR_DS_1_UV
_ERR_INT_ENA_CLR
NF_CHR_DS_UV_ER
R_INT_ENA_CLR
COMP_ERR_INT_EN
A_CLR
GRPX3_INT_ENA_CL
R
GRPX2_INT_ENA_CL
R
GRPX1_INT_ENA_CL
R
DEI_ERROR_INT_EN
A_CLR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
15
14
13
12
11
10
9
8
Reserved
R-0h
7
6
5
4
3
2
1
0
VPDMA_INT3_CLIEN
T_ENA_CLR
VPDMA_INT3_CHAN
NEL_GROUP6_ENA_
CLR
VPDMA_INT3_CHAN
NEL_GROUP5_ENA_
CLR
VPDMA_INT3_CHAN
NEL_GROUP4_ENA_
CLR
VPDMA_INT3_CHAN
NEL_GROUP3_ENA_
CLR
VPDMA_INT3_CHAN
NEL_GROUP2_ENA_
CLR
VPDMA_INT3_CHAN
NEL_GROUP1_ENA_
CLR
VPDMA_INT3_CHAN
NEL_GROUP0_ENA_
CLR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-201. intc_intr3_ena_clr1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-26
Reserved
R
0h
25
VIP2_CHR_DS_2_UV_ER
R_INT_ENA_CLR
R/W
0h
VIP2 Chroma Downsampler 2 UV Error Enable/Clear Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt
enabled Writing 0 has no effect
24
VIP2_CHR_DS_1_UV_ER
R_INT_ENA_CLR
R/W
0h
VIP2 Chroma Downsampler 1 UV Error Enable/Clear Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt
enabled Writing 0 has no effect
23
VIP1_CHR_DS_2_UV_ER
R_INT_ENA_CLR
R/W
0h
VIP1 Chroma Downsampler 2 UV Error Enable/Clear Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt
enabled Writing 0 has no effect
22
VIP1_CHR_DS_1_UV_ER
R_INT_ENA_CLR
R/W
0h
VIP1 Chroma Downsampler 1 UV Error Enable/Clear Read indicates
interrupt enable 0 = disabled 1 = enabled Writing 1 will clear interrupt
enabled Writing 0 has no effect
21
NF_CHR_DS_UV_ERR_I
NT_ENA_CLR
R/W
0h
Noise Filter Chroma Downsampler UV error Interrupt Enable/Clear
Read indicates interrupt enable 0 = disabled 1 = enabled Writing 1
will clear interrupt enabled Writing 0 has no effect
20
COMP_ERR_INT_ENA_C
LR
R/W
0h
COMP Enable/Clear Read indicates interrupt enable 0 = disabled 1
= enabled Writing 1 will clear interrupt enabled Writing 0 has no
effect
19
GRPX3_INT_ENA_CLR
R/W
0h
GRPX3 Enable/Clear Read indicates interrupt enable 0 = disabled 1
= enabled Writing 1 will clear interrupt enabled Writing 0 has no
effect
18
GRPX2_INT_ENA_CLR
R/W
0h
GRPX2 Enable/Clear Read indicates interrupt enable 0 = disabled 1
= enabled Writing 1 will clear interrupt enabled Writing 0 has no
effect
17
GRPX1_INT_ENA_CLR
R/W
0h
GRPX1 Enable/Clear Read indicates interrupt enable 0 = disabled 1
= enabled Writing 1 will clear interrupt enabled Writing 0 has no
effect
16
DEI_ERROR_INT_ENA_
CLR
R/W
0h
DEI Error Enable/Clear Read indicates interrupt enable 0 = disabled
1 = enabled Writing 1 will clear interrupt enabled Writing 0 has no
effect