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Internal Modules
257
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-105. VPDMA Channels (continued)
Channel
Description
Channel Number
Data Type
Client
vip1_mult_ancb_src7
Video Input 1 Port B
Ancillary Data Channel 7
93
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src8
Video Input 1 Port B
Ancillary Data Channel 8
94
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src9
Video Input 1 Port B
Ancillary Data Channel 9
95
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src10
Video Input 1 Port B
Ancillary Data Channel 10
96
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src11
Video Input 1 Port B
Ancillary Data Channel 11
97
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src12
Video Input 1 Port B
Ancillary Data Channel 12
98
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src13
Video Input 1 Port B
Ancillary Data Channel 13
99
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src14
Video Input 1 Port B
Ancillary Data Channel 14
100
OTHER (8)
vip1_anc_b (2)
vip1_mult_ancb_src15
Video Input 1 Port B
Ancillary Data Channel 15
101
OTHER (8)
vip1_anc_b (2)
vip1_porta_luma
Video Input 1 Port A 420
Data Luma
102
YUV (0x1, 0x2,0x7,
0x17, 0x27, 0x37)
vip1_up_y (1)
vip1_porta_chroma
Video Input 1 Port A 420
Data Chroma
103
YUV (0x5, 0x6, 0x7,
0x15, 0x16, 0x17, 0x27,
0x37)
vip1_up_uv (1)
vip1_portb_luma
Video Input 1 Port B 420
Data Luma
104
YUV (0x1, 0x2,0x7,
0x17, 0x27, 0x37)
vip1_lo_y (2)
vip1_portb_chroma
Video Input 1 Port B 420
Data Chroma
105
YUV (0x5, 0x6, 0x7,
0x15, 0x16, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_porta_rgb
Video Input 1 Port A RGB
Data
106
RGB (0x0-0x19)
vip1_up_y (1)
vip1_portb_rgb
Video Input 1 Port B RGB
Data
107
RGB (0x0-0x19)
vip1_lo_y (2)
vip2_mult_porta_src0
Video Input 2 Port A
Channel 0
108
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src1
Video Input 2 Port A
Channel 1
109
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src2
Video Input 2 Port A
Channel 2
110
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src3
Video Input 2 Port A
Channel 3
111
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src4
Video Input 2 Port A
Channel 4
112
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src5
Video Input 2 Port A
Channel 5
113
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src6
Video Input 2 Port A
Channel 6
114
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src7
Video Input 2 Port A
Channel 7
115
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src8
Video Input 2 Port A
Channel 8
116
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src9
Video Input 2 Port A
Channel 9
117
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src10
Video Input 2 Port A
Channel 10
118
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)
vip2_mult_porta_src11
Video Input 2 Port A
Channel 11
119
YUV (0x7, 0x17, 0x27,
0x37)
vip2_lo_y (21)