Texas Instruments DM38x DaVinci, User Manual

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Registers
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864 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.46 SD_VENC_l21de Register (offset = 12Ch) [reset = 0h]
SD_VENC_l21de is shown in Figure 1-541 and described in Table 1-457 .
Line 21 Data Odd Field
Figure 1-541. SD_VENC_l21de Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
L21DE0
R/W-0h
7 6 5 4 3 2 1 0
L21DE1
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-457. SD_VENC_l21de Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0h
15-8 L21DE0 R/W 0h
Closed caption data0 (even field). Specify the ASCII code of the 1st
byte to be transmitted in closed captioning for even field.
7-0 L21DE1 R/W 0h
Closed caption data1 (even field). Specify the ASCII code of the 2nd
byte to be transmitted in closed captioning for even field.