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Registers
800
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.11.6 SC_M_cfg_sc5 Register (offset = 14h) [reset = 0h]
SC_M_cfg_sc5 is shown in
and described in
Figure 1-479. SC_M_cfg_sc5 Register
31
30
29
28
27
26
25
24
Reserved
CFG_NLIN_ACC_INC_U
R-0h
R/W-0h
23
22
21
20
19
18
17
16
Reserved
CFG_SRC_W
R-0h
R/W-0h
15
14
13
12
11
10
9
8
CFG_SRC_W
Reserved
CFG_SRC_H
R/W-0h
R-0h
R/W-0h
7
6
5
4
3
2
1
0
CFG_SRC_H
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-394. SC_M_cfg_sc5 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-27
Reserved
R
0h
26-24
CFG_NLIN_ACC_INC_U
R/W
0h
This parameter is used by horizontal scaling. The 3 MSBbits of
'nlin_acc_inc' that is defined in SC_CFG11
23
Reserved
R
0h
22-12
CFG_SRC_W
R/W
0h
This parameter is a general purpose. This parameter defines the
width of the source image
11
Reserved
R
0h
10-0
CFG_SRC_H
R/W
0h
This parameter is a general purpose. This parameter defines the
height of the source image. For the interlace input.. it should be the
number of lines per field.