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Registers
450
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.42 clkc_venc_ena Register (offset = 118h) [reset = 0h]
clkc_venc_ena is shown in
and described in
.
VENC Enable Register
Figure 1-298. clkc_venc_ena Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
R-0h
7
6
5
4
3
2
1
0
Reserved
SDVENC_ENABLE
HD_VENC_D_ENABL
E
HD_VENC_A_ENABL
E
HD_VENC_D_ENABL
E
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-209. clkc_venc_ena Register Field Descriptions
Bit
Field
Type
Reset
Description
31-4
Reserved
R
0h
3
SDVENC_ENABLE
R/W
0h
SD VENC Enable 0 : Disabled 1 : Enabled
2
HD_VENC_D_ENABLE
R/W
0h
Digital Video Output 2 VENC Enable 0 : Disabled 1 : Enabled
1
HD_VENC_A_ENABLE
R/W
0h
HDCOMP VENC Enable 0 : Disabled 1 : Enabled
0
HD_VENC_D_ENABLE
R/W
0h
HDMI/Digital Video Output 1 VENC Enable 0 : Disabled 1 : Enabled