Registers
840
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.22 SD_VENC_etmg3 Register (offset = 94h) [reset = 00D3008Fh]
SD_VENC_etmg3 is shown in
and described in
Encoder Timing 3
Figure 1-517. SD_VENC_etmg3 Register
31
30
29
28
27
26
25
24
Reserved
BST_H_STP
R-0h
R/W-D3h
23
22
21
20
19
18
17
16
BST_H_STP
R/W-D3h
15
14
13
12
11
10
9
8
Reserved
BST_H_STA
R-0h
R/W-8Fh
7
6
5
4
3
2
1
0
BST_H_STA
R/W-8Fh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-433. SD_VENC_etmg3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-25
Reserved
R
0h
24-16
BST_H_STP
R/W
D3h
Color burst stop position.
15-9
Reserved
R
0h
8-0
BST_H_STA
R/W
8Fh
Color burst start position.