Texas Instruments DM38x DaVinci, User Manual

Page: 376 / 956

Registers
www.ti.com
376 SPRUHI7A – December 2012 – Revised June 2016
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.5 intc_intr0_status_ena0 Register (offset = 28h) [reset = 0h]
intc_intr0_status_ena0 is shown in Figure 1-261 and described in Table 1-172 .
Interrupt0 Enabled Register 0
Figure 1-261. intc_intr0_status_ena0 Register
31 30 29 28 27 26 25 24
SDVENC_INT_ENA DVO2_INT2_ENA DVO2_INT1_ENA DVO2_INT0_ENA Reserved DVO1_INT2_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
DVO1_INT1_ENA DVO1_INT0_ENA VIP2_PARSER_INT_
ENA
VIP1_PARSER_INT_
ENA
Reserved DEI_FMD_INT_ENA Reserved VPDMA_INT0_DESC
RIPTOR_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
VPDMA_INT0_LIST7_
NOTIFY_ENA
VPDMA_INT0_LIST7_
COMPLETE_ENA
VPDMA_INT0_LIST6_
NOTIFY_ENA
VPDMA_INT0_LIST6_
COMPLETE_ENA
VPDMA_INT0_LIST5_
NOTIFY_ENA
VPDMA_INT0_LIST5_
COMPLETE_ENA
VPDMA_INT0_LIST4_
NOTIFY_ENA
VPDMA_INT0_LIST4_
COMPLETE_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
VPDMA_INT0_LIST3_
NOTIFY_ENA
VPDMA_INT0_LIST3_
COMPLETE_ENA
VPDMA_INT0_LIST2_
NOTIFY_ENA
VPDMA_INT0_LIST2_
COMPLETE_ENA
VPDMA_INT0_LIST1_
NOTIFY_ENA
VPDMA_INT0_LIST1_
COMPLETE_ENA
VPDMA_INT0_LIST0_
NOTIFY_ENA
VPDMA_INT0_LIST0_
COMPLETE_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-172. intc_intr0_status_ena0 Register Field Descriptions
Bit Field Type Reset Description
31 SDVENC_INT_ENA R/W 0h
SD_VENC Interrupt Enabled Status Read indicates enabled status 0
= inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
30 DVO2_INT2_ENA R/W 0h
DVO2 Enabled Interrupt2 Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
29 DVO2_INT1_ENA R/W 0h
DVO2 Enabled Interrupt1 Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
28 DVO2_INT0_ENA R/W 0h
DVO2 Enabled Interrupt0 Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
27-25 Reserved R 0h
24 DVO1_INT2_ENA R/W 0h
DVO1 Enabled Interrupt2 Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
23 DVO1_INT1_ENA R/W 0h
DVO1 Enabled Interrupt1 Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
22 DVO1_INT0_ENA R/W 0h
DVO1 Enabled Interrupt0 Status Read indicates enabled status 0 =
inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
21 VIP2_PARSER_INT_ENA R/W 0h
VIP2 Parser Enabled Interrupt Status Read indicates enabled status
0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
20 VIP1_PARSER_INT_ENA R/W 0h
VIP1 Parser Enabled Interrupt Status Read indicates enabled status
0 = inactive 1 = active Writing 1 will clear interrupt Writing 0 has no
effect
19 Reserved R 0h