Texas Instruments DM38x DaVinci, User Manual

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Registers
473 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
Table 1-226. VPDMA_int0_channel0_int_mask Register Field Descriptions (continued)
Bit Field Type Reset Description
5 INT_MASK_HQ_VID3_CH
ROMA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt
signal.
4 INT_MASK_HQ_VID3_LU
MA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt
signal.
3 INT_MASK_HQ_VID2_CH
ROMA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt
signal.
2 INT_MASK_HQ_VID2_LU
MA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt
signal.
1 INT_MASK_HQ_VID1_CH
ROMA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt
signal.
0 INT_MASK_HQ_VID1_LU
MA R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int0. Write a 1 for the interrupt event to trigger the interrupt
signal.