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Registers
427
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-197. intc_intr3_status_ena1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0h
7
VPDMA_INT3_CLIENT_E
NA
R/W
0h
VPDMA INT0 Client Enabled Status Read indicates raw status 0 =
inactive 1 = active Writing 1 will set status Writing 0 has no effect
6
VPDMA_INT3_CHANNEL
_GROUP6_ENA
R/W
0h
VPDMA INT0 Channel Group6 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect
5
VPDMA_INT3_CHANNEL
_GROUP5_ENA
R/W
0h
VPDMA INT0 Channel Group5 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect
4
VPDMA_INT3_CHANNEL
_GROUP4_ENA
R/W
0h
VPDMA INT0 Channel Group4 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect
3
VPDMA_INT3_CHANNEL
_GROUP3_ENA
R/W
0h
VPDMA INT0 Channel Group3 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect
2
VPDMA_INT3_CHANNEL
_GROUP2_ENA
R/W
0h
VPDMA INT0 Channel Group3 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect
1
VPDMA_INT3_CHANNEL
_GROUP1_ENA
R/W
0h
VPDMA INT0 Channel Group1 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect
0
VPDMA_INT3_CHANNEL
_GROUP0_ENA
R/W
0h
VPDMA INT0 Channel Group0 Enabled Status Read indicates raw
status 0 = inactive 1 = active Writing 1 will set status Writing 0 has
no effect