Registers
343
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.3.6
COMP_back_color_settings Register (offset = 14h) [reset = 0h]
COMP_back_color_settings is shown in
and described in
Figure 1-235. COMP_back_color_settings Register
31
30
29
28
27
26
25
24
Reserved
BACK_CLR
R-0h
R/W-0h
23
22
21
20
19
18
17
16
BACK_CLR
R/W-0h
15
14
13
12
11
10
9
8
BACK_CLR
R/W-0h
7
6
5
4
3
2
1
0
BACK_CLR
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-143. COMP_back_color_settings Register Field Descriptions
Bit
Field
Type
Reset
Description
31-30
Reserved
R
0h
Reserved
29-0
BACK_CLR
R/W
0h
Background color in RGB format. This color will replace any pixel
with alpha value of 0. It is also output to VENCs to be used if
channel is not enabled or an underflow occurs