![background image](http://html1.mh-extra.com/html/texas-instruments/dm38x-davinci/dm38x-davinci_user-manual_1097067694.webp)
Registers
694
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.88 VPDMA_int3_client0_int_mask Register (offset = 16Ch) [reset = 0h]
VPDMA_int3_client0_int_mask is shown in
and described in
Figure 1-388. VPDMA_int3_client0_int_mask Register
31
30
29
28
27
26
25
24
INT_MASK_GRPX1_
DATA
INT_MASK_COMP_W
RBK
INT_MASK_SC_OUT
Reserved
R/W-0h
R/W-0h
R/W-0h
R-0h
23
22
21
20
19
18
17
16
Reserved
INT_MASK_SC_IN_L
UMA
INT_MASK_SC_IN_C
HROMA
INT_MASK_PIP_WRB
K
INT_MASK_DEI_SC_
OUT
Reserved
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R-0h
15
14
13
12
11
10
9
8
INT_MASK_DEI_HQ_
MV_OUT
Reserved
INT_MASK_DEI_HQ_
MV_IN
Reserved
R/W-0h
R-0h
R/W-0h
R-0h
7
6
5
4
3
2
1
0
Reserved
INT_MASK_DEI_HQ_
3_CHROMA
INT_MASK_DEI_HQ_
3_LUMA
INT_MASK_DEI_HQ_
2_CHROMA
INT_MASK_DEI_HQ_
2_LUMA
INT_MASK_DEI_HQ_
1_LUMA
INT_MASK_DEI_HQ_
1_CHROMA
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-300. VPDMA_int3_client0_int_mask Register Field Descriptions
Bit
Field
Type
Reset
Description
31
INT_MASK_GRPX1_DAT
A
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
30
INT_MASK_COMP_WRB
K
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
29
INT_MASK_SC_OUT
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
28-21
Reserved
R
0h
20
INT_MASK_SC_IN_LUMA R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
19
INT_MASK_SC_IN_CHR
OMA
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
18
INT_MASK_PIP_WRBK
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
17
INT_MASK_DEI_SC_OUT R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
16
Reserved
R
0h
15
INT_MASK_DEI_HQ_MV
_OUT
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
14-13
Reserved
R
0h
12
INT_MASK_DEI_HQ_MV
_IN
R/W
0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.
11-6
Reserved
R
0h