Texas Instruments DM38x DaVinci, User Manual

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Registers
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834 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.16 SD_VENC_irq0 Register (offset = 5Ch) [reset = 0h]
SD_VENC_irq0 is shown in Figure 1-511 and described in Table 1-427 .
IRQ Timing
Figure 1-511. SD_VENC_irq0 Register
31 30 29 28 27 26 25 24
Reserved IRQ_V_STA
R-0h R/W-0h
23 22 21 20 19 18 17 16
IRQ_V_STA
R/W-0h
15 14 13 12 11 10 9 8
Reserved IRQ_H_STA
R-0h R/W-0h
7 6 5 4 3 2 1 0
IRQ_H_STA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-427. SD_VENC_irq0 Register Field Descriptions
Bit Field Type Reset Description
31-29 Reserved R 0h
28-16 IRQ_V_STA R/W 0h
IRQ output start line
15-13 Reserved R 0h
12-0 IRQ_H_STA R/W 0h
IRQ output start pixel.