Line Related Sync Signals for OSD Interface
DTV_HS
DTV_HBI
DTV_ACTVID
hs_st_a
hs_wth_a
(n-1)th Line
nth Line (Pixels)
(n+1)th Line
4 Pixels
ST_HBI
st_cap
act_pix
VBI
VS
FID
(n-1)th Frame
VB1_WD
VB1_ST
VB2_WD
VB2_ST
1st Field
2nd Field
(n+1)th Frame
One Line
Vertical Sync Signals for OSD
nth Frame in Interlace Mode (Total Pixel per Line)
Internal Modules
130
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
The following figures illustrate the protocol of this interface.
illustrates all the signals that are
related to frame/field sync.
Figure 1-73. Vertical Sync Signals for OSD
illustrates all the signals that are related to line sync. The programmable parameters with
corresponding register names are indicated in the diagram.
Figure 1-74. Horizontal Sync-related Signal for OSD