Texas Instruments DM38x DaVinci, User Manual

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Registers
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900 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.14.7 VIP_PARSER_fiq_clear Register (offset = 18h) [reset = 0h]
VIP_PARSER_fiq_clear is shown in Figure 1-569 and described in Table 1-487 .
Clears bits in the FIQ Status
Figure 1-569. VIP_PARSER_fiq_clear Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved PORT_B_CFG_DISA
BLE_COMPLETE_CL
R
PORT_A_CFG_DISA
BLE_COMPLETE_CL
R
PORT_B_ANC_PROT
OCOL_VIOLATION_C
LR
PORT_B_YUV_PROT
OCOL_VIOLATION_C
LR
PORT_A_ANC_PROT
OCOL_VIOLATION_C
LR
PORT_A_YUV_PROT
OCOL_VIOLATION_C
LR
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
PORT_B_SRC0_SIZE
_CLR
PORT_A_SRC0_SIZE
_CLR
PORT_B_DISCONN_
CLR
PORT_B_CONN_CLR PORT_A_DISCONN_
CLR
PORT_A_CONN_CLR OUTPUT_FIFO_PRT
B_ANC_CLR
Reserved
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R-0h
7 6 5 4 3 2 1 0
OUTPUT_FIFO_PRT
B_YUV_CLR
OUTPUT_FIFO_PRT
A_ANC_CLR
Reserved OUTPUT_FIFO_PRT
A_YUV_CLR
ASYNC_FIFO_PRTB_
CLR
ASYNC_FIFO_PRTA_
CLR
PRTB_VDET_CLR PRTA_VDET_CLR
R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-487. VIP_PARSER_fiq_clear Register Field Descriptions
Bit Field Type Reset Description
31-22 Reserved R 0h
21 PORT_B_CFG_DISABLE
_COMPLETE_CLR R/W 0h Write '1' followed by '0' to Clear Port B Cfg Disable Complete FIQ
20 PORT_A_CFG_DISABLE
_COMPLETE_CLR R/W 0h Write '1' followed by '0' to Clear Port A Cfg Disable Complete FIQ
19 PORT_B_ANC_PROTOC
OL_VIOLATION_CLR R/W 0h Write '1' followed by '0' to Clear Port B ANC VPI Protocol Violation
FIQ
18 PORT_B_YUV_PROTOC
OL_VIOLATION_CLR R/W 0h Write '1' followed by '0' to Clear Port B YUV VPI Protocol Violation
FIQ
17 PORT_A_ANC_PROTOC
OL_VIOLATION_CLR R/W 0h Write '1' followed by '0' to Clear Port A ANC VPI Protocol Violation
FIQ
16 PORT_A_YUV_PROTOC
OL_VIOLATION_CLR R/W 0h Write '1' followed by '0' to Clear Port A YUV VPI Protocol Violation
FIQ
15 PORT_B_SRC0_SIZE_CL
R R/W 0h
Write '1' followed by '0' to Clear Port B Src0 Size FIQ
14 PORT_A_SRC0_SIZE_CL
R R/W 0h
Write '1' followed by '0' to Clear Port A Src0 Size FIQ
13 PORT_B_DISCONN_CLR R/W 0h
Write '1' followed by '0' to Clear Port B Link Disconnect FIQ
12 PORT_B_CONN_CLR R/W 0h
Write '1' followed by '0' to Clear Port B Link Connect FIQ
11 PORT_A_DISCONN_CLR R/W 0h
Write '1' followed by '0' to Clear Port A Link Disconnect FIQ
10 PORT_A_CONN_CLR R/W 0h
Write '1' followed by '0' to Clear Port A Link Connect FIQ
9 OUTPUT_FIFO_PRTB_A
NC_CLR R/W 0h
Write '1' followed by '0' to Clear Output FIFO Port B Ancillary
Overflow FIQ
8 Reserved R 0h
7 OUTPUT_FIFO_PRTB_Y
UV_CLR R/W 0h
Write '1' followed by '0' to Clear Output FIFO Port B Luma Overflow
FIQ
6 OUTPUT_FIFO_PRTA_A
NC_CLR R/W 0h
Write '1' followed by '0' to Clear Output FIFO Port A Ancillary
Overflow FIQ
5 Reserved R 0h