Registers
881
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.13.8 VCOMP_reg7 Register (offset = 1Ch) [reset = 0h]
VCOMP_reg7 is shown in
and described in
Figure 1-557. VCOMP_reg7 Register
31
30
29
28
27
26
25
24
Reserved
CFG_DSPLY_MAIN_Y_ORIGIN
R-0h
R/W-0h
23
22
21
20
19
18
17
16
CFG_DSPLY_MAIN_Y_ORIGIN
R/W-0h
15
14
13
12
11
10
9
8
Reserved
CFG_DSPLAY_MAIN_X_ORIGIN
R-0h
R/W-0h
7
6
5
4
3
2
1
0
CFG_DSPLAY_MAIN_X_ORIGIN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-474. VCOMP_reg7 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-28
Reserved
R
0h
Reserved
27-16
CFG_DSPLY_MAIN_Y_O
RIGIN
R/W
0h
Row origin index for the Main source picture . This source picture is
the result of any cropping by cfg_main_skip_numlines. (x..y) = (0..0)
is the top left corner of the display.
15-12
Reserved
R
0h
Reserved
11-0
CFG_DSPLAY_MAIN_X_
ORIGIN
R/W
0h
Column origin index for the Main source picture. This source picture
is the result of any cropping by cfg_main_skip_numpix. (x..y) = (0..0)
is the top left corner of the display.
