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Registers
438
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-203. clkc_clken Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
PRIM_DP_EN
R/W
0h
Primary Video Data Path Clock Enable.. 1 = Clock Enabled.. 0 =
Clock Disabled
0
VPDMA_EN
R/W
0h
VPDMA Clock Enable.. 1 = Clock Enabled.. 0 = Clock Disabled