Registers
459
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.4
VPDMA_list_stat_sync Register (offset = Ch) [reset = 0h]
VPDMA_list_stat_sync is shown in
and described in
Figure 1-304. VPDMA_list_stat_sync Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
LIST7_BUSY
LIST6_BUSY
LIST5_BUSY
LIST4_BUSY
LIST3_BUSY
LIST2_BUSY
LIST1_BUSY
LIST0_BUSY
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
15
14
13
12
11
10
9
8
Reserved
R-0h
7
6
5
4
3
2
1
0
SYNC_LISTS7
SYNC_LISTS6
SYNC_LISTS5
SYNC_LISTS4
SYNC_LISTS3
SYNC_LISTS2
SYNC_LISTS1
SYNC_LISTS0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-216. VPDMA_list_stat_sync Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
Reserved
R
0h
23
LIST7_BUSY
R
0h
The list 7 is currently running. Any attempt to load a new list to list 7
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
22
LIST6_BUSY
R
0h
The list 6 is currently running. Any attempt to load a new list to list 6
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
21
LIST5_BUSY
R
0h
The list 5 is currently running. Any attempt to load a new list to list 5
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
20
LIST4_BUSY
R
0h
The list 4 is currently running. Any attempt to load a new list to list 4
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
19
LIST3_BUSY
R
0h
The list 3 is currently running. Any attempt to load a new list to list 3
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
18
LIST2_BUSY
R
0h
The list 2 is currently running. Any attempt to load a new list to list 2
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
17
LIST1_BUSY
R
0h
The list 1 is currently running. Any attempt to load a new list to list 1
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
16
LIST0_BUSY
R
0h
The list 0 is currently running. Any attempt to load a new list to list 0
will result in the LM_ADDR and LM_ATTR registers to be locked
until the list is complete and this value goes to 0.
15-8
Reserved
R
0h
7
SYNC_LISTS7
W
0h
Writing a 1 to this field causes a sync event to fire that clears a
Control Descriptor in List 7 waiting on it.
6
SYNC_LISTS6
W
0h
Writing a 1 to this field causes a sync event to fire that clears a
Control Descriptor in List 6 waiting on it.
5
SYNC_LISTS5
W
0h
Writing a 1 to this field causes a sync event to fire that clears a
Control Descriptor in List 5 waiting on it.
4
SYNC_LISTS4
W
0h
Writing a 1 to this field causes a sync event to fire that clears a
Control Descriptor in List 4 waiting on it.