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Registers
449
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.41 clkc_venc_clksel Register (offset = 114h) [reset = 0h]
clkc_venc_clksel is shown in
and described in
VENC Clock Select Register
Figure 1-297. clkc_venc_clksel Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
DVO2_CLK_ON
DVO2_CLK_SELECT
Reserved
HD_VENC_G_CLK1X
_SELECT
R-0h
R/W-0h
R/W-0h
R-0h
R/W-0h
15
14
13
12
11
10
9
8
Reserved
VBI_HD_CLK_SELEC
T
HD_VENC_A_CLK1X
_SELECT
R-0h
R/W-0
R/W-0
7
6
5
4
3
2
1
0
Reserved
HDMI_CLK_ON
DVO1_CLK_ON
DVO1_CLK_SELECT HD_VENC_D_CLK1X
_SELECT
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-208. clkc_venc_clksel Register Field Descriptions
Bit
Field
Type
Reset
Description
31-20
Reserved
R
0h
Reserved
19
DVO2_CLK_ON
R/W
0h
Digital Video Output 2 output clock on 0 : DVO2 output clock is off
(0) 1 : DVO2 output clock is on
18
DVO2_CLK_SELECT
R/W
0h
Digital Video Output 2 output clock 0 : hd_venc_a_clk 1 :
hd_venc_a_clk/2
17
Reserved
R
0h
Reserved
16
HD_VENC_G_CLK1X_SE
LECT
R/W
0h
Digital Video Output 2 Clock 2x Select 0 : hd_venc_d_clk/2 1 :
hd_venc_a_clk/2
15-10
Reserved
R
0h
Reserved
9
VBI_HD_CLK_SELECT
R/W
0h
VBI HD Clock Select
0: HD_VENC_A VBI clk=hdcomp_clk
1: HD_VENC_A VBI clk=hdcomp_clk /2
8
HD_VENC_A_CLK1X_SE
LECT
R/W
0h
HD_VENC_A clk1x source clock
0: hdcomp_clk/2
1: hdcomp_clk
7-4
Reserved
R
0h
Reserved
3
HDMI_CLK_ON
R/W
0h
HDMI output clock on 0 : HDMI output clock is off (0) 1 : HDMI
output clock is on
2
DVO1_CLK_ON
R/W
0h
Digital Video Output 1 output clock on 0 : DVO1 output clock is off
(0) 1 : DVO1 output clock is on
1
DVO1_CLK_SELECT
R/W
0h
Digital Video Output 1 output clock 0 : hd_venc_d_clk 1 :
hd_venc_d_clk/2
0
HD_VENC_D_CLK1X_SE
LECT
R/W
0h
HD_VENC_D_DVO1 clk1x source clock 0 : hd_venc_d_clk/2 1 :
hd_venc_d_clk