Texas Instruments DM38x DaVinci, User Manual

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Registers
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524 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
Table 1-243. VPDMA_int0_list0_int_stat Register Field Descriptions (continued)
Bit Field Type Reset Description
23 INT_STAT_CONTROL_D
ESCRIPTOR_INT7 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 7. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
22 INT_STAT_CONTROL_D
ESCRIPTOR_INT6 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 6. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
21 INT_STAT_CONTROL_D
ESCRIPTOR_INT5 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 5. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
20 INT_STAT_CONTROL_D
ESCRIPTOR_INT4 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 4. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
19 INT_STAT_CONTROL_D
ESCRIPTOR_INT3 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 3. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
18 INT_STAT_CONTROL_D
ESCRIPTOR_INT2 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 2. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
17 INT_STAT_CONTROL_D
ESCRIPTOR_INT1 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 1. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
16 INT_STAT_CONTROL_D
ESCRIPTOR_INT0 W 0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 0. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
15 INT_STAT_LIST7_NOTIF
Y W 0h
A channel set by List 7 has completed and the Notify bit had been
set in the descriptor for that channel. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
14 INT_STAT_LIST7_COMP
LETE W 0h
List 7 has completed and a new list can be loaded. This event will
cause a one to be set in this register until cleared by software. Write
a 1 to this field to clear the value.
13 INT_STAT_LIST6_NOTIF
Y W 0h
A channel set by List 6 has completed and the Notify bit had been
set in the descriptor for that channel. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
12 INT_STAT_LIST6_COMP
LETE W 0h
List 6 has completed and a new list can be loaded. This event will
cause a one to be set in this register until cleared by software. Write
a 1 to this field to clear the value.
11 INT_STAT_LIST5_NOTIF
Y W 0h
A channel set by List 5 has completed and the Notify bit had been
set in the descriptor for that channel. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
10 INT_STAT_LIST5_COMP
LETE W 0h
List 5 has completed and a new list can be loaded. This event will
cause a one to be set in this register until cleared by software. Write
a 1 to this field to clear the value.
9 INT_STAT_LIST4_NOTIF
Y W 0h
A channel set by List 4 has completed and the Notify bit had been
set in the descriptor for that channel. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.