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Registers
578
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-261. VPDMA_int1_client1_int_stat Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
14
INT_STAT_NF_420_Y_IN
W
0h
The client interface nf_420_y_in has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
13
INT_STAT_NF_422_IN
W
0h
The client interface nf_422_in has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
12
INT_STAT_GRPX3_ST
W
0h
The client interface grpx3_st has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
11
INT_STAT_GRPX2_ST
W
0h
The client interface grpx2_st has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
10
INT_STAT_GRPX1_ST
W
0h
The client interface grpx1_st has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
9
INT_STAT_VIP2_UP_UV
W
0h
The client interface vip2_up_uv has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
8
INT_STAT_VIP2_UP_Y
W
0h
The client interface vip2_up_y has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
7
INT_STAT_VIP2_LO_UV
W
0h
The client interface vip2_lo_uv has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
6
INT_STAT_VIP2_LO_Y
W
0h
The client interface vip2_lo_y has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.