Texas Instruments DM38x DaVinci, User Manual

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Registers
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826 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.8 SD_VENC_dtvs2 Register (offset = 1Ch) [reset = 0h]
SD_VENC_dtvs2 is shown in Figure 1-503 and described in Table 1-419 .
DTV Sync Timing 2
Figure 1-503. SD_VENC_dtvs2 Register
31 30 29 28 27 26 25 24
Reserved DTV_VS_V_STP
R-0h R/W-0h
23 22 21 20 19 18 17 16
DTV_VS_V_STP
R/W-0h
15 14 13 12 11 10 9 8
Reserved DTV_VS_V_STA
R-0h R/W-0h
7 6 5 4 3 2 1 0
DTV_VS_V_STA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-419. SD_VENC_dtvs2 Register Field Descriptions
Bit Field Type Reset Description
31-29 Reserved R 0h
28-16 DTV_VS_V_STP R/W 0h
DTV VSYNC output stop line.
15-13 Reserved R 0h
12-0 DTV_VS_V_STA R/W 0h
DTV VSYNC output start line.