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Registers
777
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.9.23 HD_VENC_D_cfg22 Register (offset = 58h) [reset = 0h]
HD_VENC_D_cfg22 is shown in
and described in
Compositor IF Control Register
Figure 1-459. HD_VENC_D_cfg22 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
OSD_AVST_V1
R/W-0h
15
14
13
12
11
10
9
8
OSD_AVST_V1
Reserved
R/W-0h
R-0h
7
6
5
4
3
2
1
0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-372. HD_VENC_D_cfg22 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
Reserved
R
0h
Reserved
23-12
OSD_AVST_V1
R/W
0h
In progressive mode. it defines the first active line in a frame. In
interlace mode. it defines the first active line of first field in a frame
(The line number starts at 0)
11-0
Reserved
R
0h
Reserved