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Registers
789
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.10.7 nf_reg6 Register (offset = 18h) [reset = 00000F0Fh]
nf_reg6 is shown in
and described in
.
Figure 1-470. nf_reg6 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
PURE_WHITE_THRESHOLD
R-0h
R/W-Fh
7
6
5
4
3
2
1
0
Reserved
PURE_BLACK_THRESHOLD
R-0h
R/W-Fh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-384. nf_reg6 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-14
Reserved
R
0h
13-8
PURE_WHITE_THRESH
OLD
R/W
Fh
A tile is considered pure white if all pixel values are above
pure_white_threshold.
7-6
Reserved
R
0h
5-0
PURE_BLACK_THRESH
OLD
R/W
Fh
A tile is considered pure black if all pixel values are below
pure_black_threshold.