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Registers
867
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.49 SD_VENC_scctl1 Register (offset = 14Ch) [reset = 00210019h]
SD_VENC_scctl1 is shown in
and described in
Sub-carrier Frequency Control 1
Figure 1-544. SD_VENC_scctl1 Register
31
30
29
28
27
26
25
24
SCP2
R/W-21h
23
22
21
20
19
18
17
16
SCP2
R/W-21h
15
14
13
12
11
10
9
8
SCP1
R/W-19h
7
6
5
4
3
2
1
0
SCP1
R/W-19h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-460. SD_VENC_scctl1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
SCP2
R/W
21h
Sub-carrier frequency parameter 2. Default is 33. Fsc = (SCP0 +
SCP1/SCP2) * Fin / 1024
15-0
SCP1
R/W
19h
Sub-carrier frequency parameter 1. Default is 25.