Registers
458
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.3
VPDMA_list_attr Register (offset = 8h) [reset = 0h]
VPDMA_list_attr is shown in
and described in
.
Figure 1-303. VPDMA_list_attr Register
31
30
29
28
27
26
25
24
Reserved
LIST_NUM
R-0h
R/W-0h
23
22
21
20
19
18
17
16
Reserved
STOP
RDY
LIST_TYPE
R-0h
W-0h
R-0h
R/W-0h
15
14
13
12
11
10
9
8
LIST_SIZE
R/W-0h
7
6
5
4
3
2
1
0
LIST_SIZE
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-215. VPDMA_list_attr Register Field Descriptions
Bit
Field
Type
Reset
Description
31-27
Reserved
R
0h
26-24
LIST_NUM
R/W
0h
The list number that should be assigned to the list located at
LIST_ADDR. If the list is still active this will block all future list writes
until the list is available.
23-21
Reserved
R
0h
20
STOP
W
0h
This bit is written with the LIST_NUMBER field to stop a list. When
this bit is written a one the list specified by the LIST_NUMBER is
sent a stop signal and will finish the current frame of transfers and
then free the list resources.
19
RDY
R
0h
This bit is low when a new list cannot be written to the LIST_ADDR
register. The reasons this bit would be low are at initial startup if the
LIST_MANAGER State Machine image has not completed loading. It
also would be low if the last write to the LIST_ATTR attempted to
start a list that is currently active. When this bit is low any writes to
the list address register will cause access to not be accepted until
this bit has set by the previous list having completed.
18-16
LIST_TYPE
R/W
0h
The type of list that has been generated. 0: Normal List 1: Self-
Modifying List 2: List Doorbell Others Reserved for future use
15-0
LIST_SIZE
R/W
0h
Number of 128 bit word in the new list of descriptors. Writes to this
register will activate the list in the list stack of the list manager and
begin transfer of the list into VPDMA. This size can not be 0.
