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C
H
R
_
U
S
_
P
2
DEI
VCOMP
CSC_HD1
CSC_SD
GRPX
(0)
NF
CHR_DS
(NF)
SC_2
SC_1
SC_5
(WRBK)
CHR_US_AUX
GRPX
(1)
GRPX
(2)
HD
VENC_D
(DVO1)
SD
VENC
OCP
MMR
I/F
SD
DAC
VIN1
VIN0
VBI
Data
BLEND
COMP
L4
32 bit
L3_1
128 bit (2D)
4
2
2
P
4
2
2
P
4
2
2
P
4
2
2
P
4
2
2
P
422P
420T
4
2
2
P
4
2
0
T
422T
420T
422P
420T
RGB
RGB
R
G
B
R
G
B
R
G
B
4
2
0
T
C
S
C
_
W
B
2
Primary
Input
Path
(HQ)
Aux
Input
Path
(LC)
BLEND
HD
VENC_D
(DVO2)
422P
420T
422P
420T
420T
422P
420 Semi-planar tiled/
non-tiled (separate Luma
and Chroma buffers).
Cb/Cr interleaved in
Chroma buffer.
422 Interleave non-tiled
(Luma and Chroma
Interleaved in the same
buffer).
RGB
All types of RGB formats
described in VPDMA
section.
L3_2
128 bit (2D)
VPDMA
422T
420T
422-444
444-422
422-444
422-444
VBI IF
In
d
e
p
e
n
d
e
n
t
T
ra
n
s
c
o
d
e
In
p
u
t
P
a
th
2
422T
420T
In
d
e
p
e
n
d
e
n
t
T
ra
n
s
c
o
d
e
In
p
u
t
P
a
th
1
CHR_DS1
CSC_VIP1
SC_4
422-444
444-422
VIP_PARSER1
CHR_DS0
RGB
CHR_DS1
CSC_VIP0
SC_3
422-444
444-422
VIP_PARSER0
CHR_DS0
RGB
CSC_HD0
C
H
R
_
U
S
_
P
1
C
H
R
_
U
S
_
P
0
4
2
0
/2
T
4
2
0
/2
T
4
2
0
/2
T
4
1
2
3
4
5
6
7
8
VPI Control Addresses
1,2,3,4,5,6,7,8
SC_M/GRPX
CIG
cf
BLEND
sc_m_wrbk_select
vcomp_pip_select
1/2 3
4
5 6/7
1
2
3
0
1
vcomp_main
disable
3
2
1
dvo2_select
1
3
2 4-7
sdvenc_select
1
0
1
0
1
0
nf_bypass
422S
422 Semi-planar tiled/
non-tiled (separate Luma
and Chroma buffers).
Cb/Cr interleaved in
Chroma buffer.
422S
422S
C
H
R
_
U
S
_
S
E
C
0
C
H
R
_
U
S
_
S
E
C
1
7
8
9
6
4
12
13
14
15
16
1/2
3
20/21
24
23
22
19
5
10 11
18
VOUT1
DT
C1
VOUT0
DT
C0
Configuration inputs from
Control Module
Internal Modules
253
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.13.4 VPDMA and HDVPSS
The HDVPSS is shown in
with each of the VPDMA clients numbered at the top.
Figure 1-169. Block Diagram