Registers
844
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.26 SD_VENC_ccsc0 Register (offset = ACh) [reset = 0037011Dh]
SD_VENC_ccsc0 is shown in
and described in
CVBS Color Space Conversion 0
Figure 1-521. SD_VENC_ccsc0 Register
31
30
29
28
27
26
25
24
Reserved
CCSCB0
R-0h
R/W-37h
23
22
21
20
19
18
17
16
CCSCB0
R/W-37h
15
14
13
12
11
10
9
8
Reserved
CCSCA0
R-0h
R/W-11Dh
7
6
5
4
3
2
1
0
CCSCA0
R/W-11Dh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-437. SD_VENC_ccsc0 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-29
Reserved
R
0h
28-16
CCSCB0
R/W
37h
Coefficients of color space converter for CVBS. s6.6
15-13
Reserved
R
0h
12-0
CCSCA0
R/W
11Dh
Coefficients of color space converter for CVBS. s6.6