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Registers
896
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-484. VIP_PARSER_port_b Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8
ENABLE
R/W
0h
0 = Disable
1 = Enable
7
CLR_ASYNC_FIFO_RD
R/W
0h
0 = Normal
1 = Clear Async FIFO Read Logic
6
CLR_ASYNC_FIFO_WR
R/W
0h
0 = Normal
1 = Clear Async FIFO Write Logic
5-4
CTRL_CHAN_SEL
R/W
0h
PORT B supports on 8b mode. Always write 0 to this field.
The anc_chan_sel_8b register is used to select the Luma or Chroma
channel from which Ancillary Data is taken.
3-0
SYNC_TYPE
R/W
0h
0000 = embedded sync single YUV stream
0001 = embedded sync 2x multiplexed YUV stream
0010 = embedded sync 4x multiplexed YUV stream
0011 = embedded sync line multiplexed YUV stream
0100 = discrete sync single YUV stream
0101 = embedded sync single RGB stream
0110 = reserved
0111 = reserved
1000 = reserved
1001 = reserved
1010 = discrete sync single 24b RGB stream