Texas Instruments DM38x DaVinci, User Manual

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Registers
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632 SPRUHI7A – December 2012 – Revised June 2016
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Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-279. VPDMA_int2_client0_int_stat Register Field Descriptions (continued)
Bit Field Type Reset Description
18 INT_STAT_PIP_WRBK W 0h
The client interface pip_wrbk has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
17 INT_STAT_DEI_SC_OUT W 0h
The client interface dei_sc_out has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
16 Reserved R 0h
15 INT_STAT_DEI_HQ_MV_
OUT W 0h
The client interface dei_hq_mv_out has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
14-13 Reserved R 0h
12 INT_STAT_DEI_HQ_MV_
IN W 0h
The client interface dei_hq_mv_in has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
11-6 Reserved R 0h
5 INT_STAT_DEI_HQ_3_C
HROMA W 0h
The client interface dei_hq_3_chroma has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having sent the End of Frame signal to the
receiving module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
4 INT_STAT_DEI_HQ_3_L
UMA W 0h
The client interface dei_hq_3_luma has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having sent the End of Frame signal to the
receiving module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
3 INT_STAT_DEI_HQ_2_C
HROMA W 0h
The client interface dei_hq_2_chroma has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having sent the End of Frame signal to the
receiving module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
2 INT_STAT_DEI_HQ_2_L
UMA W 0h
The client interface dei_hq_2_luma has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having sent the End of Frame signal to the
receiving module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.