Texas Instruments DM38x DaVinci, User Manual

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Registers
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690 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.86 VPDMA_int3_channel6_int_mask Register (offset = 164h) [reset = 0h]
VPDMA_int3_channel6_int_mask is shown in Figure 1-386 and described in Table 1-298 .
Figure 1-386. VPDMA_int3_channel6_int_mask Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved
R-0h
15 14 13 12 11 10 9 8
Reserved
R-0h
7 6 5 4 3 2 1 0
Reserved INT_MASK_OTHER
R-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-298. VPDMA_int3_channel6_int_mask Register Field Descriptions
Bit Field Type Reset Description
31-1 Reserved R 0h
0 INT_MASK_OTHER R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int3. Write a 1 for the interrupt event to trigger the interrupt
signal.