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Registers
892
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-482. VIP_PARSER_port_a Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8
ENABLE
R/W
0h
0 = Disable Port
1 = Enable Port
7
CLR_ASYNC_FIFO_RD
R/W
0h
0 = Normal
1 = Clear Async FIFO Read Logic
6
CLR_ASYNC_FIFO_WR
R/W
0h
0 = Normal
1 = Clear Async FIFO Write Logic
5-4
CTRL_CHAN_SEL
R/W
0h
Embedded Sync Only In 8b mode.. there is only one channel on
data[7:0]. In 16b mode.. there are two channels. The Luma Channel
is on data[15:8]. The Chroma Channel is on data[7:0]. In 24b mode..
there are three channels. The R channel is on data[23:16].. the G
channel is on [15:8].. and the B channel is on data[7:0].
00 = Use data[7:0] to extract control codes.
01 = Use data[15:8] to extract control codes.
10 = Use data[23:16] to extract control codes.
11 = Undefined
In 16b and 24b modes.. this register is also used to select the
channel from which Ancillary Data is extracted. The Ancillary Data
channel must be the same as the control code channel. For 8b
mode.. the anc_chan_sel_8b register is used to select the Luma or
Chroma channel from which Ancillary Data is taken.
3-0
SYNC_TYPE
R/W
0h
0000 = embedded sync single 4:2:2 YUV stream
0001 = embedded sync 2x multiplexed 4:2:2 YUV stream
0010 = embedded sync 4x multiplexed 4:2:2 YUV stream
0011 = embedded sync line multiplexed 4:2:2 YUV stream
0100 = discrete sync single 4:2:2 YUV stream
0101 = embedded sync single RGB stream or single 444 YUV
stream
0110 = reserved
0111 = reserved
1000 = reserved
1001 = reserved
1010 = discrete sync single 24b RGB stream