Internal Modules
266
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
As stated, the above 25 interrupts are replicated four times. Each group has a separate mask register and
status register (described in
to
). At HDVPSS level, these four groups are
connected to the four external interrupts (described in
to
). As such, the
overall interrupt mechanism for software is two-tierd.
In the previous table, the “channel_group”, “client” and “descriptor” interrupts are actually a set of
additional interrupts. When software receives an interrupt from a “channel_group,” “client,” or “descriptor” it
must read the appropriate register within the VPDMA (described in
to
and use
to determine the actual interrupt.
Table 1-109. HDVPSS Interrupt Sources
Interrupt
Interrupt Group
Description
channel_aux_in
channel_group5
The last read DMA transaction has occurred for channel aux_in and the
channel is free to be updated for the next transfer. This will fire before the
destination has received the data as it will have just been stored in the internal
buffer. The client comp_wrbk will now accept a new descriptor from the List
Manager.
channel_grpx1
channel_group0
The last read DMA transaction has occurred for channel grpx1 and the channel
is free to be updated for the next transfer. This will fire before the destination
has received the data as it will have just been stored in the internal buffer. The
client grpx1_data will now accept a new descriptor from the List Manager.
channel_grpx1_clut
channel_group1
The last write DMA transaction has completed for channel grpx1_clut. All data
from the channel has been sent and received by the external memory. If a new
channel has not been setup for the client grpx1_clut_clt then the client will be
fully empty at this point.
channel_grpx1_stencil
channel_group1
The last read DMA transaction has occurred for channel grpx1_stencil and the
channel is free to be updated for the next transfer. This will fire before the
destination has received the data as it will have just been stored in the internal
buffer. The client grpx1_st will now accept a new descriptor from the List
Manager.
channel_grpx2
channel_group0
The last read DMA transaction has occurred for channel grpx2 and the channel
is free to be updated for the next transfer. This will fire before the destination
has received the data as it will have just been stored in the internal buffer. The
client grpx2_data will now accept a new descriptor from the List Manager.
channel_grpx2_clut
channel_group1
The last write DMA transaction has completed for channel grpx2_clut. All data
from the channel has been sent and received by the external memory. If a new
channel has not been setup for the client grpx2_clut_clt then the client will be
fully empty at this point.
channel_grpx2_stencil
channel_group1
The last read DMA transaction has occurred for channel grpx2_stencil and the
channel is free to be updated for the next transfer. This will fire before the
destination has received the data as it will have just been stored in the internal
buffer. The client grpx2_st will now accept a new descriptor from the List
Manager.
channel_grpx3
channel_group0
The last read DMA transaction has occurred for channel grpx3 and the channel
is free to be updated for the next transfer. This will fire before the destination
has received the data as it will have just been stored in the internal buffer. The
client grpx3_data will now accept a new descriptor from the List Manager.
channel_grpx3_clut
channel_group1
The last write DMA transaction has completed for channel grpx3_clut. All data
from the channel has been sent and received by the external memory. If a new
channel has not been setup for the client grpx3_clut_clt then the client will be
fully empty at this point.
channel_grpx3_stencil
channel_group1
The last read DMA transaction has occurred for channel grpx3_stencil and the
channel is free to be updated for the next transfer. This will fire before the
destination has received the data as it will have just been stored in the internal
buffer. The client grpx3_st will now accept a new descriptor from the List
Manager.
channel_hq_mv
channel_group0
The last read DMA transaction has occurred for channel hq_mv and the
channel is free to be updated for the next transfer. This will fire before the
destination has received the data as it will have just been stored in the internal
buffer. The client dei_hq_mv_in will now accept a new descriptor from the List
Manager.
channel_hq_mv_out
channel_group0
The last write DMA transaction has completed for channel hq_mv_out. All data
from the channel has been sent and received by the external memory. If a new
channel has not been setup for the client dei_hq_mv_out then the client will be
fully empty at this point.