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Registers
555
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.41 VPDMA_int1_channel4_int_stat Register (offset = B0h) [reset = 0h]
VPDMA_int1_channel4_int_stat is shown in
and described in
Figure 1-341. VPDMA_int1_channel4_int_stat Register
31
30
29
28
27
26
25
24
INT_STAT_VIP2_MU
LT_ANCB_SRC3
INT_STAT_VIP2_MU
LT_ANCB_SRC2
INT_STAT_VIP2_MU
LT_ANCB_SRC1
INT_STAT_VIP2_MU
LT_ANCB_SRC0
INT_STAT_VIP2_MU
LT_ANCA_SRC15
INT_STAT_VIP2_MU
LT_ANCA_SRC14
INT_STAT_VIP2_MU
LT_ANCA_SRC13
INT_STAT_VIP2_MU
LT_ANCA_SRC12
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
23
22
21
20
19
18
17
16
INT_STAT_VIP2_MU
LT_ANCA_SRC11
INT_STAT_VIP2_MU
LT_ANCA_SRC10
INT_STAT_VIP2_MU
LT_ANCA_SRC9
INT_STAT_VIP2_MU
LT_ANCA_SRC8
INT_STAT_VIP2_MU
LT_ANCA_SRC7
INT_STAT_VIP2_MU
LT_ANCA_SRC6
INT_STAT_VIP2_MU
LT_ANCA_SRC5
INT_STAT_VIP2_MU
LT_ANCA_SRC4
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
15
14
13
12
11
10
9
8
INT_STAT_VIP2_MU
LT_ANCA_SRC3
INT_STAT_VIP2_MU
LT_ANCA_SRC2
INT_STAT_VIP2_MU
LT_ANCA_SRC1
INT_STAT_VIP2_MU
LT_ANCA_SRC0
INT_STAT_VIP2_MU
LT_PORTB_SRC15
INT_STAT_VIP2_MU
LT_PORTB_SRC14
INT_STAT_VIP2_MU
LT_PORTB_SRC13
INT_STAT_VIP2_MU
LT_PORTB_SRC12
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
7
6
5
4
3
2
1
0
INT_STAT_VIP2_MU
LT_PORTB_SRC11
INT_STAT_VIP2_MU
LT_PORTB_SRC10
INT_STAT_VIP2_MU
LT_PORTB_SRC9
INT_STAT_VIP2_MU
LT_PORTB_SRC8
INT_STAT_VIP2_MU
LT_PORTB_SRC7
INT_STAT_VIP2_MU
LT_PORTB_SRC6
INT_STAT_VIP2_MU
LT_PORTB_SRC5
INT_STAT_VIP2_MU
LT_PORTB_SRC4
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-253. VPDMA_int1_channel4_int_stat Register Field Descriptions
Bit
Field
Type
Reset
Description
31
INT_STAT_VIP2_MULT_
ANCB_SRC3
W
0h
The last write DMA transaction has completed for channel
vip2_mult_ancb_src3. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client vip2_anc_b then the client will be fully empty at
this point. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
30
INT_STAT_VIP2_MULT_
ANCB_SRC2
W
0h
The last write DMA transaction has completed for channel
vip2_mult_ancb_src2. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client vip2_anc_b then the client will be fully empty at
this point. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
29
INT_STAT_VIP2_MULT_
ANCB_SRC1
W
0h
The last write DMA transaction has completed for channel
vip2_mult_ancb_src1. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client vip2_anc_b then the client will be fully empty at
this point. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
28
INT_STAT_VIP2_MULT_
ANCB_SRC0
W
0h
The last write DMA transaction has completed for channel
vip2_mult_ancb_src0. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client vip2_anc_b then the client will be fully empty at
this point. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
27
INT_STAT_VIP2_MULT_
ANCA_SRC15
W
0h
The last write DMA transaction has completed for channel
vip2_mult_anca_src15. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client vip2_anc_a then the client will be fully empty at
this point. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
26
INT_STAT_VIP2_MULT_
ANCA_SRC14
W
0h
The last write DMA transaction has completed for channel
vip2_mult_anca_src14. All data from the channel has been sent and
received by the external memory. If a new channel has not been
setup for the client vip2_anc_a then the client will be fully empty at
this point. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.