![background image](http://html1.mh-extra.com/html/texas-instruments/dm38x-davinci/dm38x-davinci_user-manual_1097067147.webp)
P1
P0
P2
PIXCLK
HSYNC
DATA
VSYNC
FID
ACTVID
P1
P0
P2
PIXCLK
HSYNC
DATA
VSYNC
FID
ACTVID
Internal Modules
147
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
FID can change at this pixel or it may change later. For interlaced source, though, the FID will be inverted
for this pixel at the same time point in the next field. So, it does not really matter when FID is captured.
Many sending devices allow the location of FID changes to be programmable.
In this diagram and all others in this document, the active polarities of the interface signals can be either
high or low. For the sake of uniformity in this document, all polarities are drawn active high. Also, different
vendors have different datasheet names for the interface signals.
Figure 1-91. Type 1, First Horizontal Blanking Pixel
shows the P0 pixel being the first Chroma Channel data value in the Vertical Ancillary Data
region. HSYNC is definitely de-asserted by now since P0 is no longer in horizontal blanking. ACTVID may
or may not be active for Vertical Ancillary Data. Some devices consider these pixels to be Active (as in
non-horizontal blanking). Other devices consider only video to be ACTIVE Video.
Figure 1-92. Type 1, First Vertical Ancillary Data Pixel