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Registers
480
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-228. VPDMA_int0_channel1_int_mask Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
INT_MASK_GRPX3_STE
NCIL
R/W
0h
The interrupt for Graphics 2 Stencil should generate an interrupt on
interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the
interrupt signal.
1
INT_MASK_GRPX2_STE
NCIL
R/W
0h
The interrupt for Graphics 1 Stencil should generate an interrupt on
interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the
interrupt signal.
0
INT_MASK_GRPX1_STE
NCIL
R/W
0h
The interrupt for Graphics 0 Stencil should generate an interrupt on
interrupt vpdma_int0. Write a 1 for the interrupt event to trigger the
interrupt signal.