Registers
747
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.131 VPDMA_trans2_chroma_cstat Register (offset = 3E0h) [reset = 0h]
VPDMA_trans2_chroma_cstat is shown in
and described in
Figure 1-431. VPDMA_trans2_chroma_cstat Register
31
30
29
28
27
26
25
24
REQ_DELAY
R/W-0h
23
22
21
20
19
18
17
16
REQ_RATE
R-0h
15
14
13
12
11
10
9
8
BUSY
DMA_ACTIVE
FRAME_START
LINE_MODE
R-0h
R-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
Reserved
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-343. VPDMA_trans2_chroma_cstat Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
REQ_DELAY
R/W
0h
The minimum number of clock cycles between requests being
issued. This value is multiplied by 32 to get the actual number of
cycles.This value is only accurate for the current frame. The internal
counters used to calculate the rate are reset when a new frame
begins and the first request of a frame will go as soon as possible.
23-16
REQ_RATE
R
0h
The number of clock cycles between the last two requests issued.
This value is multiplied by 32 to get the actual number of cycles.This
value is only accurate for the current frame. The internal counters
used to calculate the rate are reset when a new frame begins.
15
BUSY
R
0h
Signals if the client is currently active. This bit is set as soon as we
the channel is received by the client from the list manager and is
cleared when the channel is cleared from the shared memory.
14
DMA_ACTIVE
R
0h
Signals if the client is currently actively sending DMA requests
13-10
FRAME_START
R/W
0h
The source of the start frame event for the client.
0 = Change in hdmi_field_id
1 = Change in dvo2_field_id
2 = RESERVED
3 = Change in value of sd_field_id
4 = Change in value of List Manager Internal Field - 0
5 = Change in value of List Manager Internal Field - 1
6 = Change in value of List Manager Internal Field - 2
7 = Start whenever channel is free
9-8
LINE_MODE
R/W
0h
Selects the output mode of the line buffer.
0: repeat lines twice each output data line gets 2 times the number
of frame lines.
1: each line once with Line Buffer Disabled.. so no mirroring. Each
line gets frame lines with identical data.
2: Each line seen once Mirroring is enabled so the top lines get the
top lines repeated at the top of the frame and the bottom lines have
the bottom lines repeated. Each line of data gets frame lines +
number of buffered lines.
3: each line once only on one line. Each data line gets number of
frame lines divided by number of buffered lines.
7-0
Reserved
R
0h
