Registers
440
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-204. clkc_rst Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
9
HDMI_DVO1_RST
R/W
0h
HDMI/DVO1 Video Encoder Reset 1 = Reset Enable 0 = Reset
Disable
8
IND_TRANS2_DP_RST
R/W
0h
Independent Transcode 2 (to VIP2) Data Path Reset 1 = Reset
Enable 0 = Reset Disable
7
IND_TRANS1_DP_RST
R/W
0h
Independent Transcode 1 (to VIP1) Data Path Reset 1 = Reset
Enable 0 = Reset Disable
6
COMP_DP_RST
R/W
0h
Compositor Data Path Reset 1 = Reset Enable 0 = Reset Disable
5
GRPX3_DP_RST
R/W
0h
Graphics 3 Data Path Reset 1 = Reset Enable 0 = Reset Disable
4
GRPX2_DP_RST
R/W
0h
Graphics 2 Data Path Reset 1 = Reset Enable 0 = Reset Disable
3
GRPX1_DP_RST
R/W
0h
Graphics 1 Data Path Reset 1 = Reset Enable 0 = Reset Disable
2
AUX_DP_RST
R/W
0h
Auxiliary Video Data Path Reset 1 = Reset Enable 0 = Reset Disable
1
PRIM_DP_RST
R/W
0h
Primary Video Data Path Reset 1 = Reset Enable 0 = Reset Disable
0
VPDMA_RST
R/W
0h
VPDMA Reset 1 = Reset Enable 0 = Reset Disable