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Registers
827
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.9 SD_VENC_dtvs3 Register (offset = 20h) [reset = 0h]
SD_VENC_dtvs3 is shown in
and described in
.
DTV Sync Timing 3
Figure 1-504. SD_VENC_dtvs3 Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
DTV_FID_H_STA
R-0h
R/W-0h
7
6
5
4
3
2
1
0
DTV_FID_H_STA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-420. SD_VENC_dtvs3 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-13
Reserved
R
0h
12-0
DTV_FID_H_STA
R/W
0h
DTV FID output toggle pixel position.