Registers
693
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-299. VPDMA_int3_client0_int_stat Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
INT_STAT_DEI_HQ_1_L
UMA
W
0h
The client interface dei_hq_1_luma has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having sent the End of Frame signal to the
receiving module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
0
INT_STAT_DEI_HQ_1_C
HROMA
W
0h
The client interface dei_hq_1_chroma has reached its current
configured interrupt event as specified by the last received control
descriptor for this client. If no control descriptor has been configured
this will default to having sent the End of Frame signal to the
receiving module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
