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Registers
569
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.45 VPDMA_int1_channel6_int_stat Register (offset = C0h) [reset = 0h]
VPDMA_int1_channel6_int_stat is shown in
and described in
Figure 1-345. VPDMA_int1_channel6_int_stat Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
R-0h
7
6
5
4
3
2
1
0
Reserved
INT_STAT_OTHER
R-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-257. VPDMA_int1_channel6_int_stat Register Field Descriptions
Bit
Field
Type
Reset
Description
31-1
Reserved
R
0h
0
INT_STAT_OTHER
W
0h
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.