Texas Instruments DM38x DaVinci, User Manual

Page: 830 / 956

Registers
www.ti.com
830 SPRUHI7A – December 2012 – Revised June 2016
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.12 SD_VENC_dtvs6 Register (offset = 2Ch) [reset = 0h]
SD_VENC_dtvs6 is shown in Figure 1-507 and described in Table 1-423 .
DTV Sync Timing 6
Figure 1-507. SD_VENC_dtvs6 Register
31 30 29 28 27 26 25 24
Reserved DTV_AVID_V_STP0
R-0h R/W-0h
23 22 21 20 19 18 17 16
DTV_AVID_V_STP0
R/W-0h
15 14 13 12 11 10 9 8
Reserved DTV_AVID_V_STA0
R-0h R/W-0h
7 6 5 4 3 2 1 0
DTV_AVID_V_STA0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-423. SD_VENC_dtvs6 Register Field Descriptions
Bit Field Type Reset Description
31-29 Reserved R 0h
28-16 DTV_AVID_V_STP0 R/W 0h
DTV AVID output stop line for fid=0.
15-13 Reserved R 0h
12-0 DTV_AVID_V_STA0 R/W 0h
DTV AVID output start line for fid=0.