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hdin
vdin
Base
V Counter
Base FID
0.25H
0.25H
hdin
vdin
Base
V Counter
Base FID
0
1
2
3
4
5
top field
1H
0.25H
0.25H
0
1
2
3
4
bottom field
1H
Internal Modules
107
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Figure 1-61. Interlaced Slave Vertical Timing (FMD = 3)
1.2.6.2.3.7.3 Slave Mode Field Detection
For slave interface mode, the field ID is detected by one of the following methods:
1. Latch FID input at VD rise edge
2. Use raw FID input
3. Use VD input as FID
4. Detect VD phase
These four modes can be selected by the FMD register.
shows the timing of each mode.