Registers
836
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.18 SD_VENC_ectl Register (offset = 84h) [reset = 0h]
SD_VENC_ectl is shown in
and described in
Encoder Control
Figure 1-513. SD_VENC_ectl Register
31
30
29
28
27
26
25
24
Reserved
R-0h
23
22
21
20
19
18
17
16
Reserved
R-0h
15
14
13
12
11
10
9
8
Reserved
FMT
R-0h
R/W-0h
7
6
5
4
3
2
1
0
Reserved
PXLR
VBIEN
BLS
SVSW
DUPS
UPS
GAM
R-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-429. SD_VENC_ectl Register Field Descriptions
Bit
Field
Type
Reset
Description
31-12
Reserved
R
0h
11-8
FMT
R/W
0h
TV scan format select. 0: 525i 1: 625i 2-15: Reserved
7
Reserved
R
0h
6
PXLR
R/W
0h
Pixel rate. Set 0 when the pixel rate is half of the VENC clock. It is
used to determine the internal pipeline delay alignment. 0: 1x 1: 2x
5
VBIEN
R/W
0h
VBI enable. 0: Off 1: On
4
BLS
R/W
0h
Blanking shape disable. When 1.. blanking shaping feature is
disabled. 0: Enable 1: Disable
3
SVSW
R/W
0h
SD vertical sync width 0: 3H 1: 2.5H
2
DUPS
R/W
0h
DAC 2x oversampling enable. 0: Off 1: On
1
UPS
R/W
0h
2x up-sampling enable. 0: Off 1: On
0
GAM
R/W
0h
Gamma correction 0: Off 1: On