Texas Instruments DM38x DaVinci, User Manual

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Registers
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372 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7.3 intc_intr0_status_raw0 Register (offset = 20h) [reset = 0h]
intc_intr0_status_raw0 is shown in Figure 1-259 and described in Table 1-170 .
Interrupt0 Raw Register 0
Figure 1-259. intc_intr0_status_raw0 Register
31 30 29 28 27 26 25 24
SDVENC_INT_RAW DVO2_INT2_RAW DVO2_INT1_RAW DVO2_INT0_RAW Reserved DVO1_INT2_RAW
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h
23 22 21 20 19 18 17 16
DVO1_INT1_RAW DVO1_INT0_RAW VIP2_PARSER_INT_
RAW
VIP1_PARSER_INT_
RAW
Reserved DEI_FMD_INT_RAW Reserved VPDMA_INT0_DESC
RIPTOR_RAW
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R-0h R/W-0h
15 14 13 12 11 10 9 8
VPDMA_INT0_LIST7_
NOTIFY_RAW
VPDMA_INT0_LIST7_
COMPLETE_RAW
VPDMA_INT0_LIST6_
NOTIFY_RAW
VPDMA_INT0_LIST6_
COMPLETE_RAW
VPDMA_INT0_LIST5_
NOTIFY_RAW
VPDMA_INT0_LIST5_
COMPLETE_RAW
VPDMA_INT0_LIST4_
NOTIFY_RAW
VPDMA_INT0_LIST4_
COMPLETE_RAW
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
VPDMA_INT0_LIST3_
NOTIFY_RAW
VPDMA_INT0_LIST3_
COMPLETE_RAW
VPDMA_INT0_LIST2_
NOTIFY_RAW
VPDMA_INT0_LIST2_
COMPLETE_RAW
VPDMA_INT0_LIST1_
NOTIFY_RAW
VPDMA_INT0_LIST1_
COMPLETE_RAW
VPDMA_INT0_LIST0_
NOTIFY_RAW
VPDMA_INT0_LIST0_
COMPLETE_RAW
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-170. intc_intr0_status_raw0 Register Field Descriptions
Bit Field Type Reset Description
31 SDVENC_INT_RAW R/W 0h
SD VENC Interrupt Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
30 DVO2_INT2_RAW R/W 0h
DVO2 Interrupt2 Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
29 DVO2_INT1_RAW R/W 0h
DVO2 Interrupt1 Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
28 DVO2_INT0_RAW R/W 0h
DVO2 Interrupt0 Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
27-25 Reserved R 0h
24 DVO1_INT2_RAW R/W 0h
DVO1 Interrupt2 Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
23 DVO1_INT1_RAW R/W 0h
DVO1 Interrupt1 Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
22 DVO1_INT0_RAW R/W 0h
DVO1 Interrupt0 Status Read indicates raw status 0 = inactive 1 =
active Writing 1 will set status Writing 0 has no effect
21 VIP2_PARSER_INT_RA
W R/W 0h
VIP2 Parser Interrupt Status Read indicates raw status 0 = inactive 1
= active Writing 1 will set status Writing 0 has no effect
20 VIP1_PARSER_INT_RA
W R/W 0h
VIP1 Parser Interrupt Status Read indicates raw status 0 = inactive 1
= active Writing 1 will set status Writing 0 has no effect
19 Reserved R 0h
18 DEI_FMD_INT_RAW R/W 0h
DEI Film Mode Interrupt Status Read indicates raw status 0 =
inactive 1 = active Writing 1 will set status Writing 0 has no effect
17 Reserved R 0h
16 VPDMA_INT0_DESCRIP
TOR_RAW R/W 0h
VPDMA INT0 Descriptor Status Read indicates raw status 0 =
inactive 1 = active Writing 1 will set status Writing 0 has no effect
15 VPDMA_INT0_LIST7_NO
TIFY_RAW R/W 0h
VPDMA INT0 List7 Complete Status Read indicates raw status 0 =
inactive 1 = active Writing 1 will set status Writing 0 has no effect
14 VPDMA_INT0_LIST7_CO
MPLETE_RAW R/W 0h
VPDMA INT0 List7 Complete Status Read indicates raw status 0 =
inactive 1 = active Writing 1 will set status Writing 0 has no effect