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Registers
435
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-201. intc_intr3_ena_clr1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15-8
Reserved
R
0h
7
VPDMA_INT3_CLIENT_E
NA_CLR
R/W
0h
VPDMA INT0 Client Enable/Clear Read indicates interrupt enable 0
= disabled 1 = enabled Writing 1 will clear interrupt enabled Writing 0
has no effect
6
VPDMA_INT3_CHANNEL
_GROUP6_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group6 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect
5
VPDMA_INT3_CHANNEL
_GROUP5_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group5 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect
4
VPDMA_INT3_CHANNEL
_GROUP4_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group4 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect
3
VPDMA_INT3_CHANNEL
_GROUP3_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group3 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect
2
VPDMA_INT3_CHANNEL
_GROUP2_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group2 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect
1
VPDMA_INT3_CHANNEL
_GROUP1_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group1 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect
0
VPDMA_INT3_CHANNEL
_GROUP0_ENA_CLR
R/W
0h
VPDMA INT0 Channel Group0 Enable/Clear Read indicates interrupt
enable 0 = disabled 1 = enabled Writing 1 will clear interrupt enabled
Writing 0 has no effect